That playbook is breaking.
Not dramatically, not all at once, but in a way that’s increasingly hard to ignore. Wafer yields on the most advanced nodes are punishing. Reticle limits are real. The economics of building a 600 square millimeter monolithic die at 3nm are bad enough that even the companies that can afford it are starting to ask if there’s a better way.
There is. It’s called chiplets, and it’s already winning.
The basic idea, without the marketing
A chiplet is a small die that does one thing well. A CPU cluster. A memory controller. An IO complex. An AI accelerator. Instead of trying to put everything on one giant piece of silicon, you build several smaller dies, each optimized for its job, and you stitch them together inside a single package.
The connection between them happens through advanced packaging. Silicon interposers, organic substrates with high-density routing, 2.5D and 3D stacking, embedded bridges like Intel’s EMIB. The details vary. The principle is the same. You’re moving the integration boundary from “inside a single die” to “inside the package.”
If that sounds modest, it isn’t. It changes almost everything about how chips get designed, verified, manufactured, and tested.
Why monolithic is hurting
Let me give you the honest picture of why monolithic SoCs are getting harder to justify at the high end.
Yield is the first problem. Every defect on a wafer turns into a dead die. The bigger the die, the more defects it catches, the lower the yield. At a leading-edge node, a die over 500mm² can have yields below 50 percent. You’re throwing half your silicon in the bin before it ever ships.
Cost is the second problem. The most advanced nodes are expensive to design for. A full 3nm tapeout, including masks, IP licensing, and verification, can run past $500 million. You only do that if you genuinely need every block on the chip to be at 3nm. Most of the time, you don’t. The CPU cores might. The IO interfaces almost certainly don’t. The analog and mixed-signal stuff actively gets worse on bleeding-edge nodes.
Then there’s the reticle limit. EUV scanners can only print so much silicon in a single exposure. Once you bump against that ceiling, monolithic stops being an option even if you wanted it.
Chiplets answer all three. Smaller dies yield better. You can build each chiplet on the node that suits it. And you can build effective die areas larger than any reticle by stitching multiple chiplets together.
Where chiplets win on power and performance
This is the part that gets oversold, so let me be careful.
Chiplets don’t automatically make your chip faster or more power-efficient. In some ways they make things worse. The interconnect between dies is slower and burns more energy than equivalent on-die wiring. UCIe, BoW, and the various proprietary die-to-die interfaces are getting better, but they will probably never match the bandwidth and energy per bit of an on-die link.
So where’s the win?
The win is that you can size each chiplet for its actual workload. Your CPU complex gets the latest node. Your memory controllers stay on a mature node that handles analog circuits well. Your IO sits on something even older and cheaper. The total system uses less power than a monolithic equivalent because you stopped paying a leading-edge tax on blocks that didn’t need it.
You also get scalability that monolithic can’t touch. AMD’s EPYC lineup is the obvious example. Same compute chiplets, different counts per package, covering everything from 16 to 128 cores without designing a new die. The economics of that are unbeatable for any market that needs SKU diversity, which is most of them.
For AI accelerators, the case is even stronger. Training workloads want enormous amounts of compute and memory bandwidth sitting close together. Chiplets plus high-bandwidth memory plus 3D IC stacking is the only way anyone has figured out to deliver that at scale.
The verification problem nobody likes talking about
Here’s where it gets uncomfortable.
Designing a chiplet-based system is harder than designing a monolithic SoC. Anyone who tells you otherwise is selling something. The complexity doesn’t disappear, it migrates. It used to live inside your floorplan. Now it lives across die boundaries, in the interposer, in the package, in the firmware that brings up multiple dies in a coordinated sequence.
Verification has to follow it there.
You need to verify each chiplet standalone, which is the easy part. You need to verify the die-to-die interfaces under realistic traffic, which is harder. You need to verify the full system with all chiplets integrated, often with chiplets sourced from different design teams or even different companies. And you need to do all of that before you commit to silicon, because a chiplet you tape out and then can’t integrate is an expensive paperweight.
Power and thermal verification gets messier too. Three dies stacked vertically share a thermal envelope. Hot spots on one die affect timing on the die above it. The signoff conditions you used to verify each die in isolation may not hold once the package is assembled.
This is the part of the chiplet story that doesn’t make it into the keynote slides. It’s also the part that determines whether the program ships on time.
Testing is its own conversation
If verification is harder, testing is harder still.
The classic semiconductor test flow assumed one die per part. You probe at wafer, you package, you do final test, you ship. The decisions about which die was good enough to ship were made at one boundary, with one set of criteria.
Chiplet-based parts break that model. You need known-good die before you assemble, because if you build a package out of one bad chiplet and three good ones, you’ve thrown away three good chiplets too. The cost of bad assembly compounds.
That pushes test left. More aggressive wafer-level testing. More structural and parametric coverage before packaging. Better correlation between probe results and real silicon behavior. In a lot of cases, full functional and at-speed testing while the die is still on the wafer, which used to be considered overkill and is now the only way to make the economics work.
After assembly, you’re testing across die boundaries. Die-to-die links need to be exercised. Power integrity in the stacked package needs to be characterized. Thermal behavior under real workloads needs to be measured, often on every part, because variation between assemblies is real.
This is also where outsourced test and characterization partners earn their fees. Few companies want to build all of that capability in-house when they only ship a few product families a year.
The automotive and AI cases
Two markets are pulling chiplet adoption forward faster than anyone expected.
AI accelerators are the obvious one. The training chips coming out now are essentially impossible to build monolithically. Reticle-limited compute dies stitched together with HBM stacks, all sitting on a silicon interposer, is the standard recipe. Nvidia, AMD, the hyperscalers building their own silicon, all of them are doing some version of this. The question isn’t whether to use chiplets, it’s how aggressive to be with the packaging.
Automotive is the less obvious case, and it’s interesting because it inverts the usual logic. Automotive doesn’t need leading-edge transistors most of the time. What it needs is functional safety, long product lifetimes, and the ability to mix safety-rated blocks with general-purpose compute on the same platform. Chiplets let you do that without designing a fresh monolithic SoC for every variant. The safety-critical chiplet stays the same, certified once, reused across the lineup. The compute chiplet evolves on its own schedule.
This is going to be the dominant pattern in automotive silicon by the end of the decade. The companies that figure out the chiplet integration, verification, and qualification flow first will have a real advantage.
What this means for design teams
If you’re planning HPC chip design for 2027 or beyond at the high end of performance, you should already have a chiplet strategy. Not a slide. An actual strategy. Which blocks go on which node. How the die-to-die interfaces work. Where the standards land, particularly UCIe. How verification and test will handle multi-die signoff.
For the rest of us, monolithic isn’t dead. Most SoCs shipping today are still single-die designs, and they should be. Chiplets add cost, complexity, and supply chain risk. Below a certain performance and complexity threshold, the math doesn’t work yet.
But the threshold is moving. What was clearly chiplet territory only for hyperscalers two years ago is becoming sensible for advanced edge and automotive products today. The packaging supply chain is maturing. The standards are stabilizing. The tooling is catching up.
The shift isn’t dramatic. It’s just steady, and it’s not reversing.
The chip industry has spent forty years getting good at making one big thing. Now it’s getting good at making several smaller things and putting them together. That’s a real change in how the field works.
It’s also more interesting work.