From architecture and RTL to silicon bring-up, PQ Angels engineers chips that meet PPA targets and ship on schedule. We work across digital, Analog, and mixed-signal domains and engage at any point in your tape-out cycle.
Capabilities
Six capability areas. One delivery team
Whether you are starting from a spec or stepping in for a stalled tape-out, PQ Angels has the engineering depth to take ownership.
Our capabilities span the entire VLSI flow.
Front-End Design
RTL design, micro-architecture development, and IP integration done to silicon-grade quality. Our front-end engineers write code that passes linting, CDC, and synthesis the first time, not the third.
- RTL coding in Verilog, SystemVerilog, and VHDL
- Micro-architecture definition and trade-off analysis
- Soft IP and hard IP integration
- Low-power design techniques including clock gating and power gating
- Synthesis, CDC, RDC, and linting sign-off
Design Verification
Functional verification, simulation, and validation that closes coverage with discipline. Our verification engineers build environments that catch the bugs that escape lower-effort teams.
- UVM-based verification environment development
- Functional coverage and code coverage closure
- Assertion-based verification and formal methods
- Block, Sub-system, and full chip verification
- Power-aware and AMS verification
- Emulation and FPGA prototyping for pre-silicon validation
Analog & Digital Design
High-performance custom circuit design and validation. Our Analog team has delivered chips across CMOS and FinFET nodes for IoT, automotive, communications, and medical applications.
- Custom Analog and mixed-signal IP design
- PLL, ADC, DAC, SerDes, and power management circuits
- Schematic capture, simulation, and layout
- Process node experience across legacy and advanced nodes
- Silicon-correlated validation
Design for Test (DFT)
Scan insertion, ATPG, BIST, and test optimization that improves coverage and reduces test cost. Our DFT architects work alongside the design team from day one so test is built in, not bolted on.
- DFT architecture and planning
- Scan chain insertion and stitching
- ATPG pattern generation and fault simulation
- Memory BIST, logic BIST, and boundary scan
- JTAG and IEEE 1500 implementation
- Test compression and test pattern reduction
Physical Design
Floorplanning, placement, routing, timing closure, and sign-off across nodes from 180nm to advanced FinFET(3nm). We deliver GDSII that is clean on first physical sign-off.
- Floorplanning and power planning
- Placement, CTS, and routing
- Timing analysis and closure across PVT corners
- Signal integrity and IR drop analysis
- Physical verification: DRC, LVS, ERC, antenna
- ECO implementation and tape-out support
Post-Silicon Validation
Silicon bring-up, debugging, and characterization. When samples come back from the fab, we make sure they work as designed and produce the data your team needs for production.
- Bring-up plan creation and execution
- Characterization across voltage, frequency, and temperature
- Silicon debug and root-cause analysis
- Production test program development
- Yield analysis and reliability validation
How we engage
A flow built for tape-out predictability
Scoping and architecture review
Before we quote, we read your spec. We come back with risks, assumptions, and an effort range based on real engineering judgment, not a rate card.
Team formation
We assemble a team that matches your scope. You meet the leads before sign-off, not after.
Delivery in milestones
Every program runs on a milestone plan with sign-off gates. You always know where the work stands.
Sign-off and handover
We deliver clean GDSII, full sign-off reports, and the documentation your team needs to take over.
Post-tape-out support
Tape-out is not the finish line. We stay engaged through bring-up and characterization.
Tools and technology
- EDA: Cadence, Synopsys, Siemens EDA, Ansys
- Languages: SystemVerilog, Verilog, VHDL, UVM, e, C/C++ for testbench
- Methodologies: UPF/CPF for low power, UVM for verification, OVM where required
- Process nodes: 180nm down to advanced FinFET nodes(3nm)
- Foundries: Experience working with major foundry PDKs
- High speed bus protocols (PCIe Gen5, USB 3.2, USB4, CXL, NVLink)
- Chiplets and Package Interconnects (UCIe, MAX3 PHY and EMIB)
- ARMv7, ARMv8 and RISC-V architecture
- Memories (HBM3, LPDDR5, DRAM, FLASH and etc)
Industries we serve
- Semiconductor product companies and fabless startups
- Automotive, V2X and ADAS silicon
- Consumer electronics and mobile SoCs
- Networking, Storage, and Data Centres
- Wireless, 5G, and Spatial Computing + Edge AI IoT
- Medical and Industrial silicon
- Smart City Networking Backbone (Smart Grid, Smart Traffic Management)
FAQs
Common questions
Do you work on full tape-outs, or only on specific flow stages?
Both. Some clients hand us a full RTL-to-GDSII scope. Others bring us in for a specific stage such as DFT insertion, physical design, or verification closure. We scope accordingly.
Which process nodes do you have experience with?
Our engineers have worked on chips from 180nm down to FinFET nodes. Specific node experience depends on the team you engage. We share that detail in the proposal. (180nm, 24nm, 22 nm, 12 nm, 4nm and 3nm)
What engagement models do you offer?
Turnkey, ODC, time and material, and KPI-based delivery. Most VLSI programs use ODC or KPI-based models because they align well with tape-out timelines.
Do you sign NDAs and operate under client security policies?
Yes. We sign NDAs as standard practice and operate under client-specific security policies including air-gapped environments where required.
Have a chip program that needs a delivery partner?
Send us your spec, the deadline, and the stages you need owned.
We will respond with a scoped proposal.