About the Role
We are looking for an RTL Design Engineer experienced in digital design and micro-architecture development for ASIC/FPGA-based projects.
Job Description
- Develop RTL using Verilog/SystemVerilog
- Design and implement digital IP blocks
- Collaborate with verification and physical design teams
- Support synthesis and FPGA prototyping
Responsibilities
- RTL coding and lint clean design
- Micro-architecture implementation
- Low-power and performance optimization
- Design documentation and reviews
- Support integration and debugging
Required Skills
- Verilog/SystemVerilog expertise
- ASIC/FPGA design experience
- Knowledge of AMBA protocols preferred
- Understanding of synthesis and timing concepts
