About the Role
We are seeking a Design Verification Engineer with strong knowledge in SystemVerilog, UVM, and functional verification methodologies for complex SoC/IP verification projects.
Job Description
- Develop verification environments using SystemVerilog/UVM
- Create test plans, testcases, assertions, and coverage models
- Debug RTL and verification issues
- Work closely with RTL designers and architects
- Perform regression and coverage closure
Responsibilities
- IP/SoC level verification
- Functional and code coverage analysis
- Constraint random verification
- Protocol verification (PCIe,USB,DDR,HBM, AXI, APB, SPI, I2C, etc.)
- Automation and scripting support
Required Skills
- Strong SystemVerilog and UVM knowledge
- Experience in ASIC/SoC verification flow
- Debugging skills using simulators
- Perl/Python/Shell scripting knowledge preferred
