PQAngels Technologies Private Limited
Pre Si Design : 4 to 19 Years
Location : Benguluru,KA
Requirement : Experience in VLSI RTL Development(Verilog), Synthesis
Pre-Silicon Verification Engineer : 4 to 16 Years
Location : Bengaluru, KA
Skills : SV/UVM. ASIC/FPGA/SOC
DFT Engineer : 4 to 16 Years
Locatoion: Bengaluru, KA
Requirement: BIST verification, Scan Tests